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HT48RB8 8-Bit USB Type OTP MCU
Features
* Operating voltage: * 409615 program memory ROM * 1608 data memory RAM * HALT function and wake-up feature reduce power
fSYS=6M/12MHz: 4.4V~5.5V
* Low voltage reset function * 32 bidirectional I/O lines (max.) * 8-bit programmable timer/event counter with over-
consumption
* 8-level subroutine nesting * Up to 0.33ms instruction cycle with 12MHz system
flow interrupt
* 16-bit programmable timer/event counter and over-
flow interrupts
* Crystal oscillator (6MHz or 12MHz) * Watchdog Timer * 6 channels 8-bit A/D converter * USB1.1 low speed function * 4 endpoints supported (endpoint 0 included)
clock at VDD=5V
* Bit manipulation instruction * 15-bit table read instruction * 63 powerful instructions * All instructions in one or two machine cycles * 28-pin SOP, 48-pin SSOP package
General Description
This device is an 8-bit high performance RISC-like microcontroller designed for USB product applications. It is particularly suitable for use in products such as mice, keyboards and joystick. A HALT feature is included to reduce power consumption.
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Block Diagram
U S B D + /C L K U S B D -/D A T A V33O TM R1C M U X TM R1 fS
YS
U S B 1 .1 PS2 BP In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C
/4
P A 7 /T M R 1
TM R0 TM R0C
M U
fS X
YS
/4
P A 6 /T M R 0
E N /D IS W DTS In s tr u c tio n R e g is te r MP M U X DATA M e m o ry W D T P r e s c a le r WDT PA6 PA7 PAC In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX PA PORT A PA0~PA5 P A 6 /T M R 0 P A 7 /T M R 1 M U X S Y S C L K /4 W DT OSC
PBC STATUS PB
PORT B
P B 0 /A N 0 ~ P B 5 /A N 5 P B 6 /V R L P B 7 /V R H
A /D C o n v e rte r
PCC OSC2 OS R V V C1 ES DD SS ACC PC PDC PD
PORT C
PC0~PC7
PORT D
PD 0~PD 7
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Pin Assignment
PC5 PC4 PA3 PA2 PA1 PA0 PC0 PC1 PC2 PC3 PC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD V33O USBD+ USBDP B 0 /A N 0 P B 1 /A N 1 P B 2 /A N 2 P B 3 /A N 3 P B 4 /A N 4 P B 5 /A N 5 P B 6 /V R L P B 7 /V R H VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC2 PC0 PA0 PA1 PA2 PA3 PC4 PA4 PA5 P A 6 /T M R 0 P A 7 /T M R 1 OSC1 OSC2 RES NC NC NC NC PD4 PD5 PD6 PD7 VDD V33O USBD+ USBDP B 0 /A N 0 P B 1 /A N 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PC6 PC7 PA4 PA5 P A 6 /T M R 0 P A 7 /T M R 1 NC NC NC NC PD3 PD2 PD1 PD0 OSC1 OSC2 RES VSS P B 7 /V R H P B 6 /V R L P B 5 /A N 5 P B 4 /A N 4 P B 3 /A N 3 P B 2 /A N 2
H T48R B 8 2 8 S O P -A
H T48R B 8 4 8 S S O P -A
Pin Description
Pin Name I/O ROM Code Option Description
PA0~PA5 PA6/TMR0 PA7/TMR1
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is controlled by PAC (PA control register). Pull-high resistor options: PA0~PA7 Pull-low resistor options: PA0~PA5 Pull-low CMOS/NMOS/PMOS options: PA0~PA7 Pull-high I/O Wake up options: PA0~PA7 Wake-up CMOS/NMOS/PMOS PA6 and PA7 are pin-shared with TMR0 and TMR1 input, respectively. PA0~PA5 can be used as USB mouse X1, X2, Y1, Y2, Z1, Z2 input for mouse hardware wake-up function PA6, PA7 can be used as USB mouse button input for mouse hardware wake-up function Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). The PB can be used as analog input of the analog to digital converter (determined by options). PB6, PB7 can be used as USB mouse button input for mouse Hardware wake-up function Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit pull-high option). PD4 can be used as USB mouse button input for mouse hardware wake-up function
PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/VRL PB7/VRH
I/O
Pull-high Analog input
PD0~PD7
I/O
Pull-high
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Pin Name VSS I/O 3/4 ROM Code Option 3/4 Description Negative power supply, ground Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). PC0 can be used as USB mouse IRPT control pin for mouse hardware wake-up function Schmitt trigger reset input. Active low Positive power supply 3.3V regulator output USBD+ I/O line USBDOSC1, OSC2 are connected to an 6MHz or 12MHz Crystal/resonator (determined by software instructions) for the internal system clock.
PC0~PC7
I/O
Pull-high
RES VDD V33O USBD+ USBDOSC1 OSC2
I 3/4 O I/O I/O I O
3/4 3/4 3/4 3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 5V 5V 5V 5V 3/4 3/4 5V 5V 5V 5V 5V 5V VOL=3.4V VOL=0.4V VOL=0.4V VOL=0.4V Conditions fSYS=6MHz fSYS=12MHz No load, fSYS=6MHz No load, fSYS=12MHz No load, system HALT, USB suspend No load, system HALT, USB suspend 3/4 3/4 3/4 3/4 Min. 4.4 4.4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 12 2 5 10 Typ. 3/4 3/4 6.5 7.5 3/4 3/4 3/4 3/4 3/4 3/4 17 4 10 25 Max. 5.5 5.5 12 16 250 230 0.3VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4
Ta=25C Unit V V mA mA mA mA V V V V mA mA mA mA
VDD IDD1 IDD2 ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 IOL1 IOL2 IOL3 IOL4
Operating Voltage Operating Current (6MHz Crystal) Operating Current (12MHz Crystal) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) I/O Port Sink Current for PB, PC1~PC7, PD I/O Port Sink Current for PB, PC1~PC7, PD I/O Port Sink Current for PA I/O Port Sink Current for PC0
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Symbol IOH1 IOH2 RPH RPL VLVR VV33O EA/D Parameter I/O Port Source Current for PC0 Test Conditions VDD 5V Conditions VOH=3.4V VOH=3.4V 3/4 3/4 3/4 IV33O=-5mA Total error Min. -8 -2 25 15 3 3.0 3/4 Typ. -16 -5 50 30 3.4 3.3 1 Max. 3/4 3/4 80 45 4.0 3.6 2 Unit mA mA kW kW V V LSB
I/O Port Source Current for PA, PB, 5V PC1~PC7, PD Pull-high Resistance for PA, PB, PC, PD Pull-low Resistance for PA1~PA5 Low Voltage Reset 3.3V Regulator Output A/D Conversion Error 5V 5V 3/4 5V 5V
A.C. Characteristics
Symbol fSYS fTIMER Parameter System Clock (Crystal OSC) Timer I/P Frequency (TMR0/TMR1) Test Conditions VDD 5V 5V 5V 5V 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 Without WDT prescaler Without WDT prescaler 3/4 Wake-up from HALT tSST System Start-up Timer Period Power-up, Watchdog Time-out from normal 3/4 3/4 Min. 6 0 15 4 3/4 1 3/4 3/4 1 3/4 Typ. Max. 3/4 3/4 31 8 1024 3/4 1024 1024 3/4 64 12 12 70 16 3/4 3/4 3/4 3/4 3/4 3/4
Ta=25C Unit MHz MHz ms ms tSYS ms tSYS tWDTOSC ms tA/D
tWDTOSC Watchdog Oscillator Period tWDT1 tWDT2 tRES Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (System Clock) External Reset Low Pulse Width
tINT tADC Note: tA/D=
Interrupt Pulse Width A/D Conversion Time
1 , fA/D=A/D clock source frequencies (6MHz, 3MHz, 1.5MHz, 0.75MHz) fA /D
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Functional Description
Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
T1 T2 T3 T4 T1 T2
incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed to the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the current program ROM page. When a control transfer takes place, an additional dummy cycle is required.
S y s te m
C lo c k
T3
T4
T1
T2
T3
T4
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
. e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
. e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
. e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution flow
Mode Initial Reset USB Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter *11 0 0 0 0 *10 0 0 0 0 *9 0 0 0 0 *8 0 0 0 0 *7 0 0 0 0 *6 0 0 0 0 *5 0 0 0 0 *4 0 0 0 0 *3 0 0 1 1 *2 0 1 0 1 *1 0 0 0 0 *0 0 0 0 0
PC+2 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits
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Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H * Location 00CH
This location is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Table location
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H .
000H 004H 008H 00CH
D e v ic e In itia liz a tio n P r o g r a m U S B In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e P ro g ra m M e m o ry L o o k - u p T a b le ( 2 5 6 w o r d s )
n00H n..H
Any location in the program memory can be used as look-up tables. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK
...H
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to .
Program memory
This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable.
Instruction TABRDC [m] TABRDL [m]
Table Location *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program counter bits
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At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return addresses are stored). Data Memory - RAM for Bank 0 The data memory is designed with 1908 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (1608). Most are read/write, but some are read only. The special function registers include the indirect addressing registers (R0;00H, R1;02H), Bank register (BP, 04H), Timer/Event Counter 0 (;0DH), Timer/Event Counter 0 control register (TMR0C;0EH), Timer/Event Counter 1 higher order byte register (TMR1H;0FH), Timer/Event Counter 1 lower order byte register (TMR1L;10H), Timer/Event Counter 1 control register (TMR1C;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register (INTC;0BH), Watchdog Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H), I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H). USB/PS2 status and control register (USC;1AH), USB endpoint interrupt status register (USR;1BH), system clock control register (SCC;1CH). A/D converter status and control register (ADSC;1DH) and A/D converter result register (ADR;1EH). The remaining space before the 20H is reserved for future expanded usage and reading these locations will get 00H. The general purpose data memory, addressed from 20H to BFH, is used for data and control information under instruction commands.
Bank 0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0.H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1.H 20H G e n e ra l P u rp o s e D a ta M e m o ry (1 6 0 B y te s ) B.H TM R0 TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC USC USR SCC ADSC ADR :U nused R e a d a s "0 0 " In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C S p e c ia l P u r p o s e D a ta M e m o ry
Bank 0 RAM mapping All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0 or MP1).
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Data Memory - RAM for Bank 1 The special function registers used in USB interface are located in RAM bank 1. In order to access Bank1 register, only the Indirect addressing pointer MP1 can be used and the Bank register BP should set to 1. The mapping of RAM bank 1 is as shown.
40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH U n d e fin e d , r e s e r v e d fo r fu tu r e e x p a n s io n ..H . I. O 0 . I. O 1 . I. O 2 . I. O 3 AW R STALL P IP E M IS C
Bank0 or Bank1 RAM data according the value of BP is set to 0 or 1 respectively. The memory pointer registers (MP0 and MP1) are 8-bit registers. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the status register. RAM bank 1 Status Register - STATUS
Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] ([02H]) will access data memory pointed to by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result 00H. Writing indirectly results in no operation. The indirect addressing pointer (MP0) always point to Bank0 RAM addresses no matter the value of Bank Register (BP). The indirect addressing pointer (MP1) can access Labels C Bits 0
This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PD flag. In addition operations related to the status register may give different results from those intended. Function
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared by system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Unused bit, read as 0 Status register
AC Z OV PD TO 3/4 3/4
1 2 3 4 5 6 7
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The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PD flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. Register Bit No. 0 1 2 INTC (0BH) 3 4 5 6 7 Label EMI EUI ET0I ET1I USBF T0F T1F 3/4 USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of INTC) will be set.
* The access of the corresponding USB FIFO from PC * The USB suspend signal from PC * The USB resume signal from PC * USB Reset signal
When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When PC Host access the FIFO of the HT48RB8, the corresponding request bit of USR is set, and a USB interrupt is triggered. So user can easy to decide which FIFO is accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When HT48RB8 receive a USB Suspend signal from Host PC, the suspend line (bit0 of USC) of the HT48RB8 is set and a USB interrupt is also triggered. Also when HT48RB8 receive a Resume signal from Host PC, the resume line (bit3 of USC) of HT48RB8 is set and a USB interrupt is triggered. Whatever there are USB reset signal is detected, the USB interrupt is triggered. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (; bit 5 of INTC), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The internal timer/even counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (;bit 6 of INTC), caused by a timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts.
Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the USB interrupt (1= enabled; 0= disabled) Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled) Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled) USB interrupt request flag (1= active; 0= inactive) Internal Timer/Event Counter 0 request flag (1= active; 0= inactive) Internal Timer/Event Counter 1 request flag (1= active; 0= inactive) Unused bit, read as 0 INTC register
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During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. a b c Interrupt Source USB interrupt Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Priority Vector 1 2 3 04H 08H 0CH Oscillator Configuration There is an oscillator circuits in the microcontroller.
OSC1
OSC2 C r y s ta l O s c illa to r
System oscillator This oscillator is designed for system clocks. The HALT mode stops the system oscillator and ignores an external signal to conserve power. A crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works within a period of approximately 72ms. The WDT oscillator can be disabled by ROM code option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), or instruction clock (system clock divided by 4), determines the ROM code option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by ROM code option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation.
The Timer/Event Counter 0/1 interrupt request flag (T0F/T1F), USB interrupt request flag (USBF), enable Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), enable USB interrupt bit (EUI) and enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EUI, ET0I and ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F, T1F, USBF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine.
S y s te m
C lo c k /4
W DT OSC
ROM Code O p tio n S e le c t
W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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Once the internal WDT oscillator (RC oscillator with a period of 31ms/5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 8ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 1s/5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for users defined flags, which can only be set to 10000 (WDTS.7~WDTS.3). If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) or 32kHz crystal oscillator (RTC OSC) is strongly recommended, since the HALT will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 WDTS register The WDT overflow under normal operation will initialize chip reset and set the status bit TO. But in the HALT mode, the overflow will initialize a warm reset and only the PC and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a HALT instruction. The software instruction include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the ROM code option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT and CLR WDT are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. The time-out periods defined in WDTS can used as wake-up period in the Mouse Hardware wake-up function. Please reference to Mouse Hardware Wake-up function description. Rev. 1.30 12 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following...
* The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected). * The contents of the on chip RAM and registers remain unchanged.
* WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
* All of the I/O ports maintain their original status. * The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PD flags are examined, the reason for chip reset can be determined. The PD flag is cleared by system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP; the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
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The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PD and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
RES
V
DD
RES
Reset circuit
HALT W DT
W a rm
R eset
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay.
VDD RES S S T T im e - o u t C h ip R eset tS
ST
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset configuration The functional unit chip reset status are shown below. PC Interrupt Prescaler WDT 000H Disable Clear Clear. After master reset, WDT begins counting
Timer/event Counter Off Reset timing chart Input/output Ports SP Input mode Points to the top of the stack
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The states of the registers is summarized in the table. Reset (Power On) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx --00 xxxx -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 11xx 0000 0100 0000 0000 0000 1000 0000 xxxx xxxx WDT Time-out (Normal Operation) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --1u uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu RES Reset (Normal Operation) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 11xx 0000 0100 0000 0000 0000 1000 0000 xxxx xxxx RES Reset (HALT) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 11xx 0000 0100 0000 0000 0000 1000 0000 xxxx xxxx WDT Time-out (HALT)* uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB-reset (Normal) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu00 0u00 01uu 0000 0000 u000 1000 0000 xxxx xxxx USB-reset (HALT) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu00 0u00 01uu 0000 0000 u000 1000 0000 xxxx xxxx
Register
TMR0 TMR0C TMR1H TMR1L TMR1C Program Counter MP0 MP1 ACC TBLP TBLH STATUS INTC WDTS PA PAC PB PBC PC PCC PD PDC AWR PIPE STALL MISC FIFO0 FIFO1 FIFO2 FIFO3 USC USR SCC ADSC ADR Note:
* stands for warm reset u stands for unchanged x stands for unknown
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Timer/Event Counter Two timer/event counters (TMR0, TMR1) are implemented in the microcontroller. The Timer/Event Counter 0 contains an 8-bit programmable count-up counter and the clock may comes from an external source or from fSYS/4. The Timer/Event Counter 1 contains an 16-bit programmable count-up counter and the clock may come from an external source or from the system clock divided by 4. Label (TMR0C) 3/4 TE TON 3/4 Bits 0~2 3 4 5 Unused bit, read as 0 To define the TMR0 active edge of Timer/Event Counter 0 (0=active on low to high; 1=active on high to low) To enable/disable timer 0 counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C register Label (TMR1C) 3/4 TE TON 3/4 Bits 0~2 3 4 5 Unused bit, read as 0 To define the TMR1 active edge of Timer/Event Counter 1 (0=active on low to high; 1=active on high to low) To enable/disable timer 1 counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C register Function Using the internal clock source, there is only 1 reference time-base for Timer/Event Counter 0. The internal clock source is coming from fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths. Using the internal clock source, there is only 1 reference time-base for Timer/Event Counter 1. The internal clock source is coming from fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths. Function
TM0 TM1
6 7
TM0 TM1
6 7
fS
YS
/4
D a ta B u s TM 1 TM 0 TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r 0 O v e r flo w to In te rru p t T im e r /E v e n t C o u n te r 0 P r e lo a d R e g is te r R e lo a d
TM R0
Timer/Event Counter 0
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D a ta B u s fS
Y S /4
TM R1 TE TM 1 TM 0 TON
TM 1 TM 0
1 6 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r
L o w B y te B u ffe r R e lo a d
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
1 6 B its T im e r /E v e n t C o u n te r (T M R 1 H /T M R 1 L )
O v e r flo w to In te rru p t
Timer/Event Counter 1 There are 2 registers related to the Timer/Event Counter 0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical registers are mapped to TMR0 location; writing TMR0 makes the starting value be placed in the Timer/Event Counter 0 preload register and reading TMR0 gets the contents of the Timer/Event Counter 0. The TMR0C is a timer/event counter control register, which defines some options. There are 3 registers related to Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing TMR1L will only put the written data to an internal lower-order byte buffer (8 bits) and writing TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L preload registers, respectively. The Timer/Event Counter 1 preload register is changed by each writing TMR1H operations. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the lower-order byte buffer, respectively. Reading the TMR1L will read the contents of the lower-order byte buffer. The TMR1C is the Timer/Event Counter 1 control register, which defines the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR0/TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the fSYS/4 (Timer0/Timer1). The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0/TMR1). The counting is based on the fSYS/4 (Timer0/Timer1). In the event count or timer mode, once the Timer/Event Counter 0/1 starts counting, it will count from the current contents in the Timer/Event Counter 0/1 to FFH or FFFFH. Once overflow occurs, the counter is reloaded from the Timer/Event Counter 0/1 preload register and generates the interrupt request flag (T0F/T1F; bit 5/6 of INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR0/TMR1 has received a transient from low to high (or high to low if the TE bits is 0) it will start counting until the TMR0/TMR1 returns to the original level and resets the TON. The measured result will remain in the Timer/Event Counter 0/1 even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the Timer/Event Counter 0/1 starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter 0/1 is reloaded from the Timer/Event Counter 0/1 preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt services. In the case of Timer/Event Counter 0/1 OFF condition, writing data to the Timer/Event Counter 0/1 preload register will also reload that data to the Timer/Event Counter 0/1. But if the Timer/Event Counter 0/1 is turned on, data written to it will only be kept in the Timer/Event Counter 0/1 preload register. The Timer/Event Counter 0/1 will still operate until overflow occurs (a Timer/Event Counter 0/1 reloading will occur at the same time). W h e n t h e Ti m e r / E ve n t C o u n t e r 0 / 1 ( r e a d i n g TMR0/TMR1) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer.
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Input/Output Ports There are 32 bidirectional input/output lines in the microcontroller, labeled from PA to PD, which are mapped to the data memory of [12H], [14H], [16H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS/NMOS/PMOS output or Schmitt trigger input with or without pull-high/low resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS/NMOS/PMOS configurations can be selected (NMOS and PMOS are available for PA only). These control registers are mapped to locations 13H, 15H, 17H and 19H. After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high/low options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H or 18H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. There are pull-high/low (PA only) options available for I/O lines. Once the pull-high/low option of an I/O line is selected, the I/O line have pull-high/low resistor. Otherwise, the pull-high/low resistor is absent. It should be noted that a non-pull-high/low I/O line operating in input mode will cause a floating state. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state.
V C o n tr o l B it
DD
D a ta B u s
D
PH
Q CK QB S PA PB PB PC PD PG 0~ 0 /A 6 /V 0~ 0~ 0~ PA N R PC PD PG 5 , P A 6 /T M R 0 , P A 7 /T M R 1 0 ~ P B 5 /A N 5 L , P B 7 /V R H 7 7 2
W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D a ta B it Q D CK QB S PL M U X P A W a k e - u p O p tio n
W r ite D a ta R e g is te r
P A O u tp u t C o n fig u r a tio n R e a d D a ta R e g is te r P A W a k e -u p P A 6 /T M R 0 P A 7 /T M R 1 AN 0~AN 5,VR L,VR H
Input/output ports
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Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
V 3 .3 V 3 .0 V
* The low voltage (0.9V~VLVR) has to remain in their
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
LVR
original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function.
* The LVR uses the OR function with the external
RES signal to perform chip reset. Note:
V 5 .5 V
0 .9 V
VOPR is the voltage range for proper chip operation at 4MHz system clock.
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low voltage reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode.
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Suspend Wake-Up Remote Wake-Up If there is no signal on signal bus is over 3ms, the HT48RB8 will go into suspend mode . The Suspend line (bit 0 of USC) will be set to 1 and a USB interrupt is triggered to indicate the HT48RB8 should jump to suspend state to meet the 500mA USB suspend current spec. In order to meet the 500mA suspend current, the firmware should disable the USB clock by clear the USBCKEN (bit3 of the SCC) to 0. The suspend current is about 400mA. Also the user can further decrease the suspend current to 250mA by set the SUSP2 (bit4 of the SCC). But if the SUSP2 is set, the user make sure cannot enable the LVR OPT option, otherwise the HT48RB8 will be reset. When the resume signal is sent out by the host, the HT48RB8 will wake up the by USB interrupt and the Resume line (bit 3 of USC) is set. In order to make HT48RB8 work properly, the firmware must set the USBCKEN (bit 3 of SCC) to 1 and clear the SUSP2 (bit4 of the SCC). Since the Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line (bit 0 of USC) is going to 0. So when the MCU is detecting the Suspend line (bit0 of USC), the Resume line should be remembered and token into consideration. After finishing the resume signal, the suspend line will go inactive and a USB interrupt is triggered. The following is the timing diagram
SUSPEND U S B R e s u m e S ig n a l
The device with remote wake up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of USC). Once the USB Host receive the wake-up signal from HT48RB8. it will send a Resume signal to device. The timing as follow:
SUSPEND M in . 1 U S B C L K RMW K
M in .2 .5 m s
U S B R e s u m e S ig n a l
U S B _ IN T
To Configure the ADC Block The HT48RB8 has built-in a 8-bit A/D converter with 6 channels (PB0~PB5). In order to make the A/D converter more flexibility, there are two mode: External Reference voltage and Internal Reference voltage. It can easy to configure by setting the ADREF (bit 6 of USR). For External Reference voltage, the reference voltage of the A/D converter comes from external PB6/VRL and PB7/VRH pins. Otherwise, the reference voltage is coming from the VDD and VSS of MCU. PB0~PB5 is the 6-channels input of the A/D converter, it can easy to define which channel is converting by configuring ACS2~ACS0 (bit 2~0 of ADSC). Also there are four converter clock source to be selected by setting ADCS1 (bit 4 of ADSC), ADCS0 ( bit 3 of ADSC). Once the ADON (bit 6 of ADSC) is set and send the start pulse through START (bit 5 of ADSC). The A/D converter will be in operation. There are EOCB (bit 7 of ADSC) to indicate whether the A/D converter is busy or not. The EOCB is clear when the conversion is completed. The user can read the converter data by reading the register ADR. In order to meet 500uA suspend current spec. . The user should disable the A/D by clearing ADON before jump to suspend mode.
U S B _ IN T
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The following is A/D converter timing diagrams
T1 ADON 0 A /D START 0 C o n v e r s io n S ta r ts A /D C o n v e r s io n S ta r ts N o rm a l M o d e
D7
0
A /D
C o n v e r s io n
0 or1
A /D
C o n v e r s io n
0 or1
D0 1 EOCB P o w e r_ d o w n
A /D
C o n v e r s io n T im e
0 or1
A /D
C o n v e r s io n T im e
0 or1
A /D
C o n v e r s io n . in is h e d
A /D
C o n v e r s io n . in is h e d
USB Interface and A/D Converter There are 7 registers, including AWR (address + remote wake up; 42H in bank 1), STALL (43H in bank 1), PIPE (44H in bank 1), MISC (46H in bank 1), FIFO0 (48H in bank 1), FIFO1 (49H in bank 1), FIFO2 (4AH in bank 1) and FIFO3 (4BH in bank 1) used for the USB function. AWR register contains current address and a remote wake up function control bit. The initial value of AWR is 00H. The address value extracted from the USB command has not to be loaded into this register until the SETUP stage being finished. AWR WKEN AD6~AD0 Bits 0 7~1 R/W W W Remote wake-up enable/disable USB device address Function
PIPE register represents whether the corresponding endpoint is accessed by host or not. This register is set only after the time when host accesses the corresponding endpoint. Only the last accessed endpoint is shown in this register. STALL register shows whether the corresponding endpoint works properly or not. As soon as the endpoint works improperly, the related bit in the STALL has to be set to 1. The STALL will be cleared by USB reset signal. PIPE EP0RW EP1RW EP2RW EP3RW 3/4 STALL STL0 STL1 STL2 STL3 3/4 Bits 0 1 2 3 7~4 Bits 0 1 2 3 7~4 R/W R R R R R R/W W W W W W Stall the endpoint 0 Stall the endpoint 1 Stall the endpoint 2 Stall the endpoint 3 Unused bit, read as 0 Endpoint 0 accessed Endpoint 1 accessed Endpoint 2 accessed Endpoint 3 accessed Unused bit, read as 0 Function Function
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HT48RB8
MISC register combines a command and status to control desired endpoint FIFO action and to show the status of wanted endpoint FIFO. The MISC will be cleared by USB reset signal. MISC REQ Bits 0 R/W Function
After setting other status of desired one in the MISC, endpoint FIFO can be reR/W quested by setting this bit to 1. After job has been done, this bit has to be cleared to 0 This bit defines the direction of data transferring between MCU and endpoint FIFO. When the TX is set to 1, this means that MCU wants to write data to endpoint FIFO. After the job has been done, this bit has to be cleared to 0 before terminatR/W ing request to represent end of transferring. For reading action, this bit has to be cleared to 0 to represent that MCU wants to read data from endpoint FIFO and has to be set to 1 after the job done. R/W Clear the requested endpoint FIFO, even the endpoint FIFO is not ready. To define which endpoint FIFO is selected, SELP1,SELP0: 00: endpoint FIFO0 R/W 01: endpoint FIFO1 10: endpoint FIFO2 11: endpoint FIFO3 It is used to show that the data in endpoint FIFO is SETUP command. This bit has to R/W be cleared by firmware. That is to say, even the MCU is busing, the device will not miss any SETUP commands from host. R R/W Read only status bit, this bit is used to indicate that the desired endpoint FIFO is ready to work. Read only status bit, it is sued to indicate that a 0-sized packet is sent from host to MCU. This bit should be cleared by firmware.
TX
1
CLEAR
2
SELP1 SELP0
4 3
SCMD
5
READY LEN0
6 7
MCU can communicate with endpoint FIFO by setting the corresponding registers, of which address is listed in the following table. After reading current data, next data will show on after 2ms. using to check endpoint FIFO status and response to MSIC register, if read/write action is still going on. Registers FIFO0 FIFO1 FIFO2 FIFO3 R/W R/W R/W R/W R/W Bank 1 1 1 1 Address 48H 49H 4AH 4BH Bit7~Bit0 Data7~Data0 Data7~Data0 Data7~Data0 Data7~Data0
There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing. Actions Read FIFO0 sequence Write FIFO1 sequence Check whether FIFO0 can be read or not Check whether FIFO1 can be written or not Read 0-sized packet sequence form FIFO0 Write 0-sized packet sequence to FIFO1 Note: MiSC Setting Flow and Status 00H(R)01H(R)delay 2ms, check 41H(R)read* from FIFO0 register and check not ready (01H)(R)03H(R)02H 0AH(R)0BH(R)delay 2ms, check 4BH(R)write* to FIFO1 register and check not ready (0BH)(R)09H(R)08H 00H(R)01H(R)delay 2ms, check 41H (ready) or 01H (not ready)(R)00H 0AH(R)0BH(R)delay 2ms, check 4BH (ready) or 0BH (not ready)(R)0AH 00H(R)01H(R)delay 2ms, check 81H(R)read once (01H)(R)03H(R)02H 0AH(R)0BH(R)delay 2ms, check 0BH(R)0FH(R)0DH(R)08H
*: There are 2ms existing between 2 reading action or between 2 writing action
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The definitions of the USB status and control register (USC; 1AH) are as shown. USC SUSP Bits 0 R/W R Function Read only, USB suspend indication. When this bit is set to 1 (set by SIE), it indicates the USB bus enters suspend mode. The USB interrupt is also triggered on any changing of this bit. USB remote wake up command. It is set by MCU to force the USB host leaving the suspend mode. When this bit is set to 1, 2ms delay for clearing this bit to 0 is needed to insure the RMWK command is accepted by SIE. USB reset indication. This bit is set/cleared by USB SIE. When the URST is set to 1, this indicates an USB reset is occurred and an USB interrupt will be initialized. USB resume indication. When the USB leaves suspend mode, this bit is set to 1 (set by SIE). This bit will appear 20ms waiting for MCU to detect. When the RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to detecting the suspend state, MCU should set USBCKEN and SUSP2 (in SCC register) to enable the SIE detecting function. The RESUME will be cleared while the SUSP is going 0. When MCU is detecting the SUSP, the RESUME (causes MCU to wake-up) should be remembered and token into consideration. Undefined bit Undefined bit This bit should be set as 1 Data for driving USBD+/CLK pin when work under 3D PS2 mouse function. (Default=1) This bit should be set as 1
RMWK
1
W
URST
2
R/W
RESUME
3
R
3/4 3/4 3/4 3/4
4 5 6 7
R R W W
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select A/D converter operation modes. The endpoint request flags (EP0IF, EP1IF, EP2IF and EP3IF) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and the USB interrupt will occur (if USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request flag has to be cleared to 0. USR EP0IF Bits 0 R/W Function
When this bit is set to 1 (set by SIE), it indicates the endpoint 0 is accessed and an R/W USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. When this bit is set to 1 (set by SIE), it indicates the endpoint 1 is accessed and an R/W USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. When this bit is set to 1 (set by SIE), it indicates the endpoint 2 is accessed and an R/W USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. When this bit is set to 1 (set by SIE), it indicates the endpoint 3 is accessed and an R/W USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. R/W This bit should be forced to 0. R/W This bit should be set as 1. The reference voltage of A/D converter is coming from the VDD and VSS of MCU R/W when this bit is set 1. Otherwise, the reference voltage of A/D converter comes from external PB6/VRL and PB7/VRH pins. (Default=1) W For ICE only, 0 for FIFO read (Default=0); 1 for FIFO write
EP1IF
1
EP2IF
2
EP3IF 3/4 3/4 ADREF FIFO-cntl
3 4 5 6 7
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There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK). SCC 3/4 USBCKEN Bits 2~0 3 R/W 3/4 R/W Undefined bits USB clock control bit. When this bit is set to 1, it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. (Default=0) Function
SUSP2 3/4 SYSCLK 3/4
4 5 6 7
This bit is used for decreasing power consumption in suspend mode. R/W In normal mode clean this bit=0 (Default=0) In HALT mode set this bit=1 for decreasing power consumption. R/W Undefined, should be cleared to 0 This bit is used to specify the system oscillator frequency used by MCU. If a 6MHz R/W crystal oscillator or resonator is used, this bit should be set to 1. If a 12MHz crystal oscillator or resonator is used, this bit should be cleared to 0 (default). 3/4 This bit should be forced to 0
The A/D converter implemented in the MCU is a 6-channel 8-bit A/D converter. The reference voltage (high reference voltage and low reference voltage) can be selected as coming from external pins (PB6/VRL and PB7/VRH) or internal power supplies of MCU (VDD and VSS). The VRL and VRH are used to set the minimal and maximal boundaries of the full-scale range of the A/D converter. If an analog inputs, VRL or VRH is not used for A/D conversion, it also can be used as a general purpose I/O line. The ADSC (A/D converter status and control register) register is used to set the configurations and A/D clock sources of A/D converter and control the operation of A/D converter. ADSC Bits Function These 3 bits are use to select one of eight A/D converter channels for the conversion. The A/D converter input channels AN0~AN5 are pin-shared with PB0~PB5. PB6/VRL and PB7/VRH are used for the A/D converter reference inputs. ACS2,ACS1,ACS0 : 000/001/010/011/100/101/110/111: AN0/AN1/AN2/AN3/AN4/AN5/VRL/VRH A/D converter clock source selection. ADCS1,ADCS0: 00: 6MHz 01: 3MHz 10: 1.5MHz 11: 0.75MHz Start the A/D conversion. (0(R)1(R)0: start, 0(R)1: reset A/D converter and A/D data register) This bit is used to control the enable/disable of A/D converter circuit. If this bit is set to 1 the A/D converter enters operating mode. Otherwise, the A/D converter will be turned-off End of A/D conversion indication. (0: end of A/D conversion)
ACS2~ACS0
2~0
ADCS1 ADCS0
4 3
START ADON EOCB
5 6 7
The A/D converter data register is used to store the result of A/D conversion. ADR D7~D0 Bits 7~0 Result of A/D conversion Function
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Mask Options The following table shows all kinds of mask option in the microcontroller. All of the mask options must be defined to ensure proper system functioning. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Chip lock bit (by bit) PA0~PA7 pull-high resistor enabled or disabled (by bit) PA0~PA5 pull down resistor enabled or disabled (by bit) PB0~PB7 pull-high resistor enabled or disabled (by nibble) PC0~PC7 pull-high resistor enabled or disabled (by nibble) PD0~PD7 pull-high resistor enabled or disabled (by nibble) LVR enable or disable WDT enable or disable WDT clock source: fSYS/4 or WDTOSC CLRWDT instruction(s): 1 or 2 PA0~PA7 output structures: CMOS/NMOS open-drain or PMOS open-drain (by bit) PA0~PA7 wake-up enabled or disabled (by bit) A/D converter enabled or disabled Option
Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications
VDD USBUSB+ VSS 0 .1 m .
5W
*
10m.
33W
*
100kW 0 .1 m . 22p.
PA0~PA7 VDD PB0~PB7 PC0~PC7 PD0~PD7
*
X1
OSC1
V33O
OSC2
1 .5 k W
0 .1 m .
5W
*
0 .1 m .
22p. 10kW
47p.*
*
0 .1 m .
*
RES
USBD47p.*
33W
* *
*
47p. 33W
VSS
USBD+
H T48R B 8
*
47p.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible Components with * are used for EMC issue. 22pF capacitances are used for resonator only.
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 CALL addr Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr
Operation Affected flag(s)
TC2 3/4 CLR [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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CLR [m].i Description Operation Affected flag(s) TC2 3/4 CLR WDT Description Operation Affected flag(s) TC2 3/4 CLR WDT1 Description TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are cleared. WDT 00H PD and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CLR WDT2 Description
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CPL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TC2 3/4 DAA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TC2 3/4 DEC [m] Description Operation Affected flag(s) TC2 3/4 DECA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0
Operation
Affected flag(s) TC2 3/4 INC [m] Description Operation Affected flag(s) TC2 3/4 INCA [m] Description Operation Affected flag(s) TC2 3/4 JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 NOP Description Operation Affected flag(s) TC2 3/4 OR A,[m] Description Operation Affected flag(s) TC2 3/4 OR A,x Description Operation Affected flag(s) TC2 3/4 ORM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
No operation No operation is performed. Execution continues with the next instruction. PC PC+1
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TC2 3/4 RET A,x Description Operation Affected flag(s) TC2 3/4 RETI Description Operation Affected flag(s) TC2 3/4 RL [m] Description Operation Affected flag(s) TC2 3/4 RLA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TC2 3/4 RLCA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TC2 3/4 RR [m] Description Operation Affected flag(s) TC2 3/4 RRA [m] Description Operation Affected flag(s) TC2 3/4 RRC [m] Description Operation TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TC2 3/4 Rev. 1.30 TC1 3/4 TO 3/4 PD 3/4 34 OV 3/4 Z 3/4 AC 3/4 C O February 10, 2003
HT48RB8
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TC2 3/4 SBC A,[m] Description Operation Affected flag(s) TC2 3/4 SBCM A,[m] Description Operation Affected flag(s) TC2 3/4 SDZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TC2 3/4 SDZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
35
February 10, 2003
HT48RB8
SET [m] Description Operation Affected flag(s) TC2 3/4 SET [m]. i Description Operation Affected flag(s) TC2 3/4 SIZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TC2 3/4 SIZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TC2 3/4 SNZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
36
February 10, 2003
HT48RB8
SUB A,[m] Description Operation Affected flag(s) TC2 3/4 SUBM A,[m] Description Operation Affected flag(s) TC2 3/4 SUB A,x Description Operation Affected flag(s) TC2 3/4 SWAP [m] Description Operation Affected flag(s) TC2 3/4 SWAPA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Rev. 1.30
37
February 10, 2003
HT48RB8
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TC2 3/4 TABRDC [m] Description Operation Affected flag(s) TC2 3/4 TABRDL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
38
February 10, 2003
HT48RB8
XOR A,[m] Description Operation Affected flag(s) TC2 3/4 XORM A,[m] Description Operation Affected flag(s) TC2 3/4 XOR A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.30
39
February 10, 2003
HT48RB8
Package Information
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E .
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
Rev. 1.30
40
February 10, 2003
HT48RB8
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a .
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
Rev. 1.30
41
February 10, 2003
HT48RB8
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 1000.1 13.0+0.5 -0.2 2.00.5 32.2+0.3 -0.2 38.20.2
Rev. 1.30
42
February 10, 2003
HT48RB8
Carrier Tape Dimensions
D
E .
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
Rev. 1.30
43
February 10, 2003
HT48RB8
D
E . W C B0
P0
P1
t
D1
P K2 A0
K1
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.00.3 16.00.1 1.750.1 14.20.1 2.0 Min. 1.5+0.25 4.00.1 2.00.1 12.00.1 16.200.1 2.40.1 3.20.1 0.350.05 25.5
Rev. 1.30
44
February 10, 2003
HT48RB8
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2003 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
45
February 10, 2003

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